An addressing scheme which allows for a variety of addressing modes while using a minimum number of address lines through the use of weighted sets of mutually independent rather than binary address lines.
In a typical random access addressing circuit, a number of binary lines are decoded and used to select one of a plurality of locations. To use a numerical example, if there are 32 elements, then 5 address lines can be used to select one and only one targeted element at a time. Also, a random access memory must have a write enable line so that the write cycle will not be initiated until the address lines have settled.
A system for reducing the number of address lines for a sequentially accessed memory will use serial addressing means such as a token ring, or shift register, to pass access from one target to the next.
One place where address lines must be used is in a light emitting diode (LED) print bar in a printer, where LED's must be selected for calibration and printing. However, the typical binary addressing circuit is not suited for this use. Most importantly, the binary circuit can select only one element at a time, while in an LED print bar, several elements, or even all elements, will have to be selected at one time under certain circumstances. Another disadvantage of a typical binary scheme is that each target element must be wired differently. For a numerical example, element 1 will have to be gated at its input to react to a 00001 input while element number 15 will have to react to a 01111. This means that the input of each element will have a different set of decoding logic, which complicates the efficiency of placing and routing gates.
What is required is an addressing scheme which can target one, several or all elements, allow all of the elements to have the same input configuration for easier placement and route of gates, operate without a write enable line and accomplish this with the fewest address lines.